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LTC2201 1 2201f 16-bit, 20msps adc the ltc ? 2201 is a 20msps, sampling 16-bit a/d converter designed for digitizing high frequen cy, wide dynamic range signals with input frequencies up to 380mhz. the input range of the adc can be optimized with the pga front end. the LTC2201 is perfect for demanding app lications, with ac performance that includes 81.6db snr and 100db spurious free dynamic range (sfdr). maximum dc specs include 5lsb inl, 1lsb dnl (no missing codes). a separate output power supply allows the cmos output swing to range from 0.5v to 3.6v. a single-ended clk input controls converter operation. an optional clock duty cycle stabilizer allows high performance at full speed with a wide range of clock duty cycles. l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. n telecommunications n receivers n cellular base stations n spectrum analysis n imaging systems n ate n sample rate: 20msps n 81.6db snr and 100db sfdr (2.5v range) n 90db sfdr at 70mhz (1.667v p-p input range) n pga front end (2.5v p-p or 1.667v p-p input range) n 380mhz full power bandwidth s/h n optional internal dither n optional data output randomizer n single 3.3v supply n power dissipation: 211mw n clock duty cycle stabilizer n out-of-range indicator n pin compatible family 25msps: ltc2203 (16-bit) 10msps: ltc2202 (16-bit) n 48-pin (7mm 7mm) qfn package C + s/h amp correction logic and shift register output drivers 16-bit pipelined adc core internal adc reference generator 1.25v common mode bias voltage clock/duty cycle control clk pga shdn dith mode rand v cm analog input 2201 ta01 d15 t t t d0 cmos outputs 0.5v to 3.6v 3.3v 3.3v sense ognd ov dd 2.2f 1f 1f 1f 1f v dd gnd adc control inputs a in + a in C of clkout+ clkoutC oe code 0 inl error (lsb) 0.0 0.5 1.0 65536 2201 ta02 C0.5 C1.0 C2.0 16384 32768 49152 C1.5 2.0 1.5 integral nonlinearity (inl) vs output code features description applications typical application
LTC2201 2 2201f top view uk package 48-lead (7mm s 7mm) plastic qfn sense 1 v cm 2 v dd 3 v dd 4 gnd 5 a in + 6 a in C 7 gnd 8 gnd 9 clk 10 gnd 11 v dd 12 36 ov dd 35 d11 34 d10 33 d9 32 d8 31 ognd 30 clkout + 29 clkout C 28 d7 27 d6 26 d5 25 ov dd 48 gnd 47 pga 46 rand 45 mode 44 oe 43 of 42 d15 41 d14 40 d13 39 d12 38 ognd 37 ov dd v dd 13 v dd 14 gnd 15 shdn 16 dith 17 d0 18 d1 19 d2 20 d3 21 d4 22 ognd 23 ov dd 24 49 exposed pad is gnd (pin 49) must be soldered to pcb board t jmax = 150c, ja = 29c/w supply voltage (v dd ) .................................. C 0.3v to 4v digital output supply voltage (ov dd ) ......... C 0.3v to 4v digital output ground voltage (ognd) ........C 0.3v to 1v analog input voltage (note 3) .....C 0.3v to (v dd + 0.3v) digital input voltage ....................C 0.3v to (v dd + 0.3v) digital output voltage ............... C 0.3v to (ov dd + 0.3v) power dissipation ............................................2000mw operating temperature range LTC2201c ............................................... 0c to 70c LTC2201i ............................................ C 40c to 85c storage temperature range ................. C 65c to 150c ov dd = v dd (notes 1 and 2) absolute maximum ratings pin configuration order information lead free finish tape and reel part marking* package description temperature range LTC2201cuk#pbf LTC2201cuk#trpbf LTC2201uk 48-lead (7mm 7mm) plastic qfn 0c to 70c LTC2201iuk#pbf LTC2201iuk#trpbf LTC2201uk 48-lead (7mm 7mm) plastic qfn C40c to 85c consult ltc marketing for parts speci? ed with wider operating temperature ranges. *the temperature grade is identi? ed by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/
LTC2201 3 2201f converter characteristics parameter conditions min typ max units resolution (no missing codes) 16 integral linearity error differential analog input (note 5) l 1.5 5 lsb differential linearity error differential analog input l 0.3 1 lsb offset error (note 6) l 2 10 mv offset drift 10 v/c gain error external reference l 0.2 1.5 %fs full-scale drift internal reference external reference 30 15 ppm/c ppm/c transition noise external reference (2.5v range, pga = 0) 1.92 lsb rms symbol parameter conditions min typ max units v in analog input range (a in + C a in C ) 3.135v v dd 3.465v 1.667 or 2.5 v p-p v in, cm analog input common mode differential input (note 7) l 1 1.25 1.5 v i in analog input leakage current 0v a in + , a in C v dd (note 9) l C1 1 a i sense sense input leakage current 0v sense v dd (note 10) l C3 3 a i mode mode pin pull-down current to gnd 10 a i oe oe pin pull-down current to gnd 10 a c in analog input capacitance sample mode clk = 0 hold mode clk = 0 10.5 1.4 pf pf t ap sample-and-hold acquisition delay time 0.9 ns t jitter sample-and-hold acquisition delay time jitter 200 fs rms cmrr analog input common mode rejection ratio 1v < (a in + = a in C ) <1.5v 80 db bw-3db full power bandwidth r s < 20 380 mhz symbol parameter conditions min typ max units snr signal-to-noise ratio 1mhz input (2.25v range, pga = 0) 1mhz input (1.667v range, pga = 1) 81.6 79.4 dbfs dbfs 5mhz input (2.5v range, pga = 0) 5mhz input (1.667v range, pga = 1) l 80 81.6 79.4 dbfs dbfs 12.5mhz input (2.5v range, pga = 0) 12.5mhz input (1.667v range, pga = 1) 81.4 79.3 dbfs dbfs 30mhz input (2.5v range, pga = 0) 30mhz input (1.667v range, pga = 1) 80.8 78.9 dbfs dbfs 70mhz input (2.5v range, pga = 0) 70mhz input (1.667v range, pga =1 ) 78.3 77.2 dbfs dbfs analog input dynamic accuracy the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. a in = C 1dbfs. (note 4) the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4) the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4)
LTC2201 4 2201f the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. a in = C 1dbfs. (note 4) dynamic accuracy symbol parameter conditions min typ max units sfdr spurious free dynamic range 2 nd or 3 rd harmonic 1mhz input (2.5v range, pga = 0) 1mhz input (1.667v range, pga = 1) 100 100 dbc dbc 5mhz input (2.5v range, pga = 0) 5mhz input (1.667v range, pga = 1) l 85 100 100 dbc dbc 12.5mhz input (2.5v range, pga = 0) 12.5mhz input (1.667v range, pga = 1) 95 100 dbc dbc 30mhz input (2.5v range, pga = 0) 30mhz input (1.667v range, pga = 1) 90 95 dbc dbc 70mhz input (2.5v range, pga = 0) 70mhz input (1.667v range, pga = 1) 85 90 dbc dbc sfdr spurious free dynamic range 4th harmonic or higher 1mhz input (2.5v range, pga = 0) 1mhz input (1.667v range, pga = 1) 100 100 dbc dbc 5mhz input (2.5v range, pga = 0) 5mhz input (1.667v range, pga = 1) l 90 100 100 dbc dbc 12.5mhz input (2.5v range, pga = 0) 12.5mhz input (1.667v range, pga = 1) 100 100 dbc dbc 30mhz input (2.5v range, pga = 0) 30mhz input (1.667v range, pga = 1) 100 100 dbc dbc 70mhz input (2.5v range, pga = 0) 70mhz input (1.667v range, pga = 1) 90 90 dbc dbc s/(n+d) signal-to-noise plus distortion ratio 1mhz input (2.5v range, pga = 0) 1mhz input (1.667v range, pga = 1) 81.5 79.3 dbfs dbfs 5mhz input (2.5v range, pga = 0) 5mhz input (1.667v range, pga = 1) l 79.7 81.5 79.3 dbfs dbfs 12.5mhz input (2.5v range, pga = 0) 12.5mhz input (1.667v range, pga = 1) 81.3 79.2 dbfs dbfs 30mhz input (2.5v range, pga = 0) 30mhz input (1.667v range, pga = 1) 80.6 78.6 dbfs dbfs 70mhz input (2.5v range, pga = 0) 70mhz input (1.667v range, pga = 1) 78.1 77 dbfs dbfs sfdr spurious free dynamic range at C 25dbfs dither off 1mhz input (2.5v range, pga = 0) 1mhz input (1.667v range, pga = 1) 105 105 dbfs dbfs 5mhz input (2.5v range, pga = 0) 5mhz input (1.667v range, pga = 1) 105 105 dbfs dbfs 12.5mhz input (2.5v range, pga = 0) 12.5mhz input (1.667v range, pga = 1) 105 105 dbfs dbfs 30mhz input (2.5v range, pga = 0) 30mhz input (1.667v range, pga = 1) 105 105 dbfs dbfs 70mhz input (2.5v range, pga = 0) 70mhz input (1.667v range, pga = 1) 100 100 dbfs dbfs
LTC2201 5 2201f parameter conditions min typ max units v cm output voltage i out = 0 1.15 1.25 1.35 v v cm output tempco i out = 0 40 ppm/c v cm line regulation 3.135v v dd 3.465v 1 mv/ v v cm output resistance 1ma | i out | 1ma 2 common mode bias characteristics symbol parameter conditions min typ max units logic inputs (clk, oe, dith, pga, shdn, rand) v ih high level input voltage v dd = 3.3v l 2v v il low level input voltage v dd = 3.3v l 0.8 v i in digital input current v in = 0v to v dd l 10 a c in digital input capacitance (note 7) 1.5 pf logic outputs ov dd = 3.3v v oh high level output voltage v dd = 3.3v i o = C10a i o = C 200a l 3.1 3.299 3.29 v v v ol low level output voltage v dd = 3.3v i o = 160a i o = 1.6ma l 0.01 0.10 0.4 v v i source output source current v out = 0v C50 ma i sink output sink current v out = 3.3v 50 ma ov dd = 2.5v v oh high level output voltage v dd = 3.3v i o = C 200a 2.49 v v ol low level output voltage v dd = 3.3v i o = 1.60ma 0.1 v ov dd = 1.8v v oh high level output voltage v dd = 3.3v i o = C 200a 1.79 v v ol low level output voltage v dd = 3.3v i o = 1.60ma 0.1 v digital inputs and digital outputs symbol parameter conditions min typ max units sfdr spurious free dynamic range at C 25dbfs dither on 1mhz input (2.5v range, pga = 0) 1mhz input (1.667v range, pga = 1) 115 115 dbfs dbfs 5mhz input (2.5v range, pga = 0) 5mhz input (1.667v range, pga = 1) 115 115 dbfs dbfs 12.5mhz input (2.5v range, pga = 0) 12.5mhz input (1.667v range, pga = 1) 115 115 dbfs dbfs 30mhz input (2.5v range, pga = 0) 30mhz input (1.667v range, pga = 1) 115 115 dbfs dbfs 70mhz input (2.5v range, pga = 0) 70mhz input (1.667v range, pga = 1) 110 110 dbfs dbfs dynamic accuracy the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. a in = C 1dbfs. (note 4) the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4) the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4)
LTC2201 6 2201f timing characteristics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltage values are with respect to gnd, with gnd and ognd shorted (unless otherwise noted). note 3: when these pin voltages are taken below gnd or above v dd , they will be clamped by internal diodes. this product can handle input currents of greater than 100ma below gnd or above v dd without latchup. note 4: v dd = 3.3v, f sample = 20mhz, input range = 2.5v p-p with differential drive (pga = 0), unless otherwise speci? ed. note 5: integral nonlinearity is de? ned as the deviation of a code from a best ? t straight line to the transfer curve. the deviation is measured from the center of the quantization band. note 6: offset error is the offset voltage measured from C 1/2lsb when the output code ? ickers between 0000 0000 0000 0000 and 1111 1111 1111 1111 in 2s complement output mode. note 7: guaranteed by design, not subject to test. note 8: recommended operating conditions. note 9: dynamic current from switched capacitor inputs is large compared to dc leakage current, and will vary with sample rate. note 10: leakage current will experience transient at power up. keep resistance < 1k. the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4) the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. a in = C1dbfs. (note 4) symbol parameter conditions min typ max units v dd analog supply voltage l 3.135 3.3 3.465 v p shdn shutdown power shdn = v dd , clk = v dd 2m w ov dd output supply voltage l 0.5 3.6 v i vdd analog supply current l 64 80 ma p dis power dissipation l 211 264 mw power requirements symbol parameter conditions min typ max units f s sampling frequency l 1 20 mhz t l clk low time duty cycle stabilizer off duty cycle stabilizer on l l 20 5 25 25 500 500 ns ns t h clk high time duty cycle stabilizer off duty cycle stabilizer on l l 20 5 25 25 500 500 ns ns t ap sample-and-hold aperture delay 0.9 ns t d clk to data delay c l = 5pf (note 7) l 1.3 3.1 4.9 ns t c clk to clkout delay c l = 5pf (note 7) l 1.3 3.1 4.9 ns t skew data to clkout skew c l = 5pf (note 7) l C 0.6 0 0.6 ns data access time bus relinquish time c l = 5pf (note 7) (note 7) l l 5 5 15 15 ns ns pipeline latency 7 cycles
LTC2201 7 2201f integral nonlinearity (inl) vs output code differential nonlinearity (dnl) vs output code ac grounded input histogram (256k samples) code 0 inl error (lsb) 0.0 0.5 1.0 65536 2201 g01 C0.5 C1.0 C2.0 16384 32768 49152 C1.5 2.0 1.5 code 0 C1.0 dnl error (lsb) C0.8 C0.4 C0.2 0.0 1.0 0.4 16384 32768 2201 g02 C0.6 0.6 0.8 0.2 49152 65536 output code 32812 0 count 10000 20000 30000 40000 50000 60000 32816 32820 32824 32828 2201 g03 32832 t ap analog input t h t d t c t l n C 7 n C 6 n C 5 n C 4 n C 3 clk clkout + clkout C d0-d15, of 2201 td01 n + 1 n + 2 n + 4 n + 3 n timing diagram typical performance characteristics sfdr vs input level, f in = 5mhz, pga = 0, dither off sfdr vs input level, f in = 5mhz, pga = 0, dither on input level (dbfs) C70 sfdr (dbc and dbfs) 80 100 120 2201 g04 60 40 C60 C50 C40 C30 C20 C10 0 20 0 140 input level (dbfs) C70 sfdr (dbc and dbfs) 80 100 120 2201 g05 60 40 C60 C50 C40 C30 C20 C10 0 20 0 140 sfdr vs input level, f in = 12.7mhz, pga = 0, dither off input level (dbfs) C70 sfdr (dbc and dbfs) 80 100 120 2201 g06 60 40 C60 C50 C40 C30 C20 C10 0 20 0 140
LTC2201 8 2201f sfdr vs input level, f in = 12.7mhz, pga = 0, dither on sfdr vs input level, f in = 30.1mhz, pga = 0, dither off sfdr vs input level, f in = 30.1mhz, pga = 0, dither on input level (dbfs) C70 sfdr (dbc and dbfs) 80 100 120 2201 g07 60 40 C60 C50 C40 C30 C20 C10 0 20 0 140 input level (dbfs) C80 sfdr (dbc and dbfs) 80 100 120 2201 g08 60 40 C70 C60 C50 C40 C30 C20 C10 0 20 0 140 input level (dbfs) C70 sfdr (dbc and dbfs) 80 100 120 2201 g09 60 40 C60 C50 C40 C30 C20 C10 0 20 0 140 typical performance characteristics sfdr vs input level, f in = 70.1mhz, pga = 0, dither off sfdr vs input level, f in = 70.1mhz, pga = 0, dither on sfdr (hd2 or hd3) vs input frequency snr vs input frequency input level (dbfs) C70 C60 C50 C40 C30 C20 C10 0 sfdr (dbc and dbfs) 80 100 120 2201 g10 60 40 20 0 140 input level (dbfs) C70 sfdr (dbc and dbfs) 80 100 120 2201 g11 60 40 C60 C50 C40 C30 C20 C10 0 20 0 140 input frequency (mhz) 0 sfdr (dbc) 85 90 95 60 100 2201 g12 80 75 70 20 40 80 100 105 110 pga = 1 pga = 0 input frequency (mhz) 0 73 snr (dbfs) 74 76 77 78 80 82 2201 g13 75 40 20 100 120 60 140 79 80 81 pga = 0 pga = 1 snr and sfdr vs supply voltage (v dd ), f in = 5mhz supply voltage (v) 2.8 snr sfdr (dbfs) 95 100 105 3.4 3.5 2201 g14 90 85 2.9 3.0 3.1 3.2 3.3 3.6 80 75 110 sfdr lower limit upper limit snr i vdd vs sample rate, 5mhz sine wave, C1dbfs sample rate (msps) 0 i vdd (ma) 62 65 68 16 2201 g15 59 56 53 4 8 12 20
LTC2201 9 2201f normalized full scale vs temperature, internal reference, 5 units offset voltage vs temperature, 5 units sfdr vs input common mode voltage, f in = 5mhz, C1dbfs, pga = 0 temperature (c) C40 0.99 normalized full scale 0.995 1 1.005 1.01 C20 0 20 40 2201 g16 60 80 temperature (?c) C40 offset voltage (mv) 2 4 6 20 60 2201 g17 0 C2 C20 0 40 80 C4 C6 input common mode voltage (v) 0.5 60 sfdr (dbc) 70 80 90 0.75 1 1.25 1.50 2201 g18 1.75 100 110 65 75 85 95 105 2 typical performance characteristics time after wake-up or clock start (s) 0 full-scale error (%) 0.2 0.6 1.0 400 2201 g19 C0.2 C0.6 0 0.4 0.8 C0.4 C0.8 C1.0 10050 200150 300 350 450 250 500 time from wake-up or clock start (s) 0 full-scale error (%) 1 3 5 800 2201 g20 C1 C3 0 2 4 C2 C4 C5 200100 400300 600 700 900 500 1000 mid-scale settling after wake up from shutdown or starting encode clock full-scale settling after wake up from shutdown or starting encode clock
LTC2201 10 2201f sense (pin 1): reference mode select and external refer- ence input. tie sense to v dd with 1k or less to select the internal 2.5v bandgap reference. an external reference of 2.5v or 1.25v may be used; both reference values will set a full scale adc range of 2.5v (pga = 0). v cm (pin 2): 1.25v output. optimum voltage for input com- mon mode. must be bypassed to ground with a minimum of 2.2f. ceramic chip capacitors are recommended. v dd (pins 3, 4, 12, 13, 14): 3.3v analog supply pin. bypass to gnd with 0.1f ceramic chip capacitors. gnd (pins 5, 8, 9, 11, 15, 48, 49): adc power ground. a in + (pin 6): positive differential analog input. a in C (pin 7): negative differential analog input. clk (pin 10): clock input. the hold phase of the sample- and-hold circuit begins on the falling edge. the output data may be latched on the rising edge of clk. shdn (pin 16): power shutdown pin. shdn = low results in normal operation. shdn = high results in powered down analog circuitry and the digital outputs are placed in a high impedance state. dith (pin 17): internal dither enable pin. dith = low disables internal dither. dith = high enables internal dither. refer to internal dither section of this data sheet for details on dither operation. d0-d15 (pins 18-22, 26-28, 32-35 and 39-42): digital outputs. d15 is the msb. ognd (pins 23, 31 and 38): output driver ground. ov dd (pins 24, 25, 36, 37): positive supply for the output drivers. bypass to ground with 0.1f capacitors. clkout C (pin 29): data valid output. clkout C will toggle at the sample rate. latch the data on the falling edge of clkout C . clkout + (pin 30): inverted data valid output. clkout + will toggle at the sample rate. latch the data on the rising edge of clkout + . of (pin 43): over/under flow digital output. of is high when an over or under ? ow has occurred. oe (pin 44): output enable pin. low enables the digital output drivers. high puts digital outputs in hi-z state. mode (pin 45): output format and clock duty cycle stabilizer selection pin. connecting mode to 0v selects offset binary output format and disables the clock duty cycle stabilizer. connecting mode to 1/3v dd selects offset binary output format and enables the clock duty cycle sta- bilizer. connecting mode to 2/3v dd selects 2s complement output format and enables the clock duty cycle stabilizer. connecting mode to v dd selects 2s complement output format and disables the clock duty cycle stabilizer. rand (pin 46): digital output randomization selection pin. rand low results in normal operation. rand high selects d1-d15 to be exclusive-ored with d0 (the lsb). the output can be decoded by again applying an xor operation between the lsb and all other bits. the mode of operation reduces the effects of digital output interference. pga (pin 47): programmable gain ampli? er control pin. low selects a front-end gain of 1, input range of 2.5v p-p . high selects a front-end gain of 1.5, input range of 1.667v p-p . gnd (exposed pad, pin 49): adc power ground. the ex- posed pad on the bottom of the package must be soldered to ground. pin functions
LTC2201 11 2201f figure 1. functional block diagram adc clocks low jitter clock driver dither signal generator first pipelined adc stage fifth pipelined adc stage fourth pipelined adc stage second pipelined adc stage clk correction logic and shift register dith m0de ognd clkout + clkout C of d15 d14 ov dd d1 d0 2201 f01 input s/h a in C a in + third pipelined adc stage output drivers control logic pga rand shdn t t t v dd gnd pga sense v cm buffer adc reference voltage reference range select oe block diagram
LTC2201 12 2201f dynamic performance signal-to-noise plus distortion ratio the signal-to-noise plus distortion ratio [s/(n+d)] is the ratio between the rms amplitude of the fundamental input frequency and the rms amplitude of all other frequency components at the adc output. the output is band lim- ited to frequencies above dc to below half the sampling frequency. signal-to-noise ratio the signal-to-noise (snr) is the ratio between the rms amplitude of the fundamental input frequency and the rms amplitude of all other frequency components, except the ? rst ? ve harmonics. total harmonic distortion total harmonic distortion is the ratio of the rms sum of all harmonics of the input signal to the fundamental itself. the out-of-band harmonics alias into the frequency band between dc and half the sampling frequency. thd is expressed as: thd = C 20log ( (v 2 2 + v 3 2 + v 4 2 + ... v n 2 )/v 1 ) where v 1 is the rms amplitude of the fundamental fre- quency and v 2 through v n are the amplitudes of the second through nth harmonics. intermodulation distortion if the adc input signal consists of more than one spectral component, the adc transfer function nonlinearity can produce intermodulation distortion (imd) in addition to thd. imd is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. if two pure sine waves of frequencies fa and fb are ap- plied to the adc input, nonlinearities in the adc transfer function can create distortion products at the sum and difference frequencies of mfa nfb, where m and n = 0, 1, 2, 3, etc. for example, the 3rd order imd terms include (2fa + fb), (fa + 2fb), (2fa - fb) and (fa - 2fb). the 3rd order imd is de? ned as the ratio of the rms value of either input tone to the rms value of the largest 3rd order imd product. spurious free dynamic range (sfdr) the ratio of the rms input signal amplitude to the rms value of the peak spurious spectral component expressed in dbc. sfdr may also be calculated relative to full scale and expressed in dbfs. full power bandwidth the full power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3db for a full scale input signal. aperture delay time the time from when clk reaches 0.45 of v dd to the instant that the input signal is held by the sample-and- hold circuit. aperture delay jitter the variation in the aperture delay time from conversion to conversion. this random variation will result in noise when sampling an ac input. the signal to noise ratio due to the jitter alone will be: snr jitter = C 20log (2 ? f in ? t jitter ) applications information
LTC2201 13 2201f converter operation the LTC2201 is a cmos pipelined multistep con verter with a front-end pga. as shown in figure 1, the converter has ? ve pipelined adc stages; a sampled analog input will result in a digitized value seven cycles later (see the timing diagram section). the analog input is differential for improved common mode noise immunity and to maximize the input range. additionally, the differential input drive will reduce even order harmonics of the sample-and-hold circuit. each pipelined stage shown in figure 1 contains an adc, a reconstruction dac and an interstage ampli? er. in op- eration, the adc quantizes the input to the stage and the quantized value is subtracted from the input by the dac to produce a residue. the residue is ampli? ed and output by the residue ampli? er. successive stages operate out of phase so that when odd stages are outputting their residue, the even stages are acquiring that residue and vice versa. the phase of operation is determined by the state of the clk input pin. when clk is high, the analog input is sampled differen- tially directly onto the input sample-and-hold capacitors, inside the input s/h shown in the block diagram. at the instant that clk transitions from high to low, the voltage on the sample capacitors is held. while clk is low, the held input voltage is buffered by the s/h ampli? er which drives the ? rst pipelined adc stage. the ? rst stage acquires the output of the s/h ampli? er during the low phase of clk. when clk goes back high, the ? rst stage produces its residue which is acquired by the second stage. at the same time, the input s/h goes back to acquiring the analog input. when clk goes low, the second stage produces its residue which is acquired by the third stage. an identi- cal process is repeated for the third and fourth stages, resulting in a fourth stage residue that is sent to the ? fth stage for ? nal evaluation. each adc stage following the ? rst has additional range to accommodate ? ash and ampli? er offset errors. results from all of the adc stages are digitally delayed such that the results can be properly combined in the correction logic before being sent to the output buffer. sample/hold operation and input drive sample/hold operation figure 2 shows an equivalent circuit for the LTC2201 cmos differential sample and hold. the differ ential analog inputs are sampled directly onto sampling capacitors (c sample ) through nmos transitors. the capacitors shown attached to each input (c parasitic ) are the summation of all other capacitance associated with each input. figure 2. equivalent input circuit LTC2201 clk 2201 f02 v dd v dd r parasitic 3 r parasitic 3 a in + a in C c parasitic 1.4pf c parasitic 1.4pf c sample 9.1pf c sample 9.1pf r on 20 r on 20 applications information during the sample phase when clk is high, the nmos transistors connect the analog inputs to the sampling capacitors and they charge to, and track the differential input voltage. when clk transitions from high to low, the sampled input voltage is held on the sampling capacitors. during the hold phase when clk is high, the sampling capacitors are disconnected from the input and the held voltage is passed to the adc core for processing. as clk transitions from low to high, the inputs are reconnected to the sampling capacitors to acquire a new sample. since the sampling capacitors still hold the previous sample, a charging glitch proportional to the change in voltage between samples will be seen at this time at the input of the converter. if the change between the last sample and
LTC2201 14 2201f the new sample is small, the charging glitch seen at the input will be small. if the input change is large, such as the change seen with input frequencies near nyquist, then a larger charging glitch will be seen. common mode bias the adc sample-and-hold circuit requires differential drive to achieve speci? ed performance. each input may swing 0.625v for the 2.5v range (pga = 0) or 0.417v for the 1.667v range (pga = 1), around a common mode voltage of 1.25v. the v cm output pin (pin 2) is designed to provide the common mode bias level. v cm can be tied directly to the center tap of a transformer to set the dc input level or as a reference level to an op amp differential driver circuit. the v cm pin must be bypassed to ground close to the adc with 2.2f or greater. input drive impedence as with all high performance, high speed adcs the dy- namic performance of the LTC2201 can be in? uenced by the input drive circuitry, particularly the second and third harmonics. source impedance and input reac- tance can in? uence sfdr. at the rising edge of clk the sample and hold circuit will connect the 9.1pf sampling capacitor to the input pin and start the sampling period. the sampling period ends when clk falls, holding the sampled input on the sampling capacitor. ideally, the input circuitry should be fast enough to fully charge the sampling capacitor during the sampling period 1/(2f clk ); however, this is not always possible and the incomplete settling may degrade the sfdr. the sampling glitch has been designed to be as linear as possible to minimize the effects of incomplete settling. for the best performance it is recommended to have a source impedance of 100 or less for each input. the source impedance should be matched for the differential inputs. poor matching will result in higher even order harmonics, especially the second. input drive circuits figure 3 shows the LTC2201 being driven by an rf trans- former with a center-tapped secondary. the secondary center tap is dc biased with v cm , setting the adc input signal at its optimum dc level. figure 3 shows a 1:1 turns ratio transformer. other turns ratios can be used; however, as the turns ratio increases so does the impedance seen by the adc. source impedance greater than 50 can reduce the input bandwidth and increase high frequency distor- tion. a disadvantage of using a transformer is the loss of low frequency response. most small rf transformers have poor performance at frequencies below 1mhz. figure 3. single-ended to differential conversion using a transformer. recommended for input frequencies from 1mhz to 100mhz LTC2201 analog input t1 = coilcraft wbci-it or ma/com etc1-1t. resistors, capacitors are 0402 package size, except 2.2f. 2201 f03 0.1f 2.2f 12pf 12pf 12pf 0.1f t1 1:1 25 25 25 25 v cm a in + a in C figure 4. using a transmission line balun transformer. recommended for input frequencies from 50mhz to 250mhz 0.1f a in + a in C 4.7pf 2.2f 4.7pf 4.7pf v cm analog input 0.1f 0.1f t1 1:1 t1 = ma/com etc1-1-13. resistors, capacitors are 0402 package size, except 2.2f. 2201 f04 25 25 25 10 10 25 LTC2201 center-tapped transformers provide a convenient means of dc biasing the secondary; however, they often show poor balance at high input frequencies, resulting in large 2nd order harmonics. figure 4 shows transformer coupling using a transmis- sion line balun transformer. this type of transformer has much better high frequency response and balance than ? ux coupled center tap transformers. coupling capacitors are added at the ground and input primary terminals to allow the secondary terminals to be biased at 1.25v. applications information
LTC2201 15 2201f figure 5 demonstrates the use of an ltc1994 differential ampli? er to convert a single ended input signal into a differential input signal. the advantage of this method is that it provides low frequency input response; however, the limited gain bandwidth of any op amp will limit the sfdr at high input frequencies. the internal programmable gain ampli? er provides the internal reference voltage for the adc. this ampli? er has very stringent settling requirements and is not accessible for external use. figure 5. dc coupled input with differential ampli? er v cm 2201 f05 C C + + cm lt1994 499 100pf 100pf 100pf 2.2 f 499 523 25 25 499 53.6 a in + a in C LTC2201 figure 6. reference circuit pga 1.25v sense v cm buffer internal adc reference range select and gain control 2.5v bandgap reference 2.2f tie to v dd to use internal 2.5v reference or input for external 2.5v reference or input for external 1.25v reference 2201 f06 LTC2201 figure 7. a 2.5v range adc with an external 2.5v reference v cm sense 1.25v 3.3v 2.2f 2.2f 1f 2201 f07 lt1461-2.5 2 6 4 LTC2201 the sense pin can be driven 5% around the nominal 2.5v or 1.25v external reference input. this adjustment range can be used to trim the adc gain error or other system gain errors. when selecting the internal reference, the sense pin should be tied to v dd as close to the converter as possible. if the sense pin is driven externally it should be bypassed to ground as close to the device as possible with at least a 1f ceramic capacitor. applications information the 25 resistors and 12pf capacitor on the analog inputs serve two purposes: isolating the drive circuitry from the sample-and-hold charging glitches and limiting the wideband noise at the converter input. reference operation figure 6 shows the LTC2201 reference circuitry consisting of a 2.5v bandgap reference, a programmable gain ampli- ? er and control circuit. the LTC2201 has three modes of reference operation: internal reference, 1.25v external reference or 2.5v external reference. to use the internal reference, tie the sense pin to v dd . to use the external reference, simply apply either a 1.25v or 2.5v reference voltage to the sense input pin. both 1.25v and 2.5v applied to sense will result in a full scale range of 2.5v p-p (pga = 0). a 1.25v output, v cm , is provided for a common mode bias for input drive circuitry. an external bypass capacitor is required for the v cm output. this provides a high frequency low impedance path to ground for internal and external circuitry. this is also the compensation capacitor for the reference; it will not be stable without this capacitor. the minimum value required for stability is 2.2f.
LTC2201 16 2201f in applications where jitter is critical, such as when digi- tizing high input frequencies, use as large an amplitude as possible. it is also helpful to drive the clk pin with a low-jitter high frequency source which has been divided down to the appropriate sample rate. if the adc is clocked with a sinusoidal signal, ? lter the clk signal to reduce wideband noise and distortion products generated by the source. maximum and minimum conversion rates the maximum conversion rate for the LTC2201 is 20msps. for the adc to operate properly the clk signal should have a 50% (10%) duty cycle. each half cycle must have at least 20ns for the LTC2201 internal circuitry to have enough settling time for proper operation. an on-chip clock duty cycle stabilizer may be activated if the input clock does not have a 50% duty cycle. this circuit uses the falling edge of clk pin to sample the analog input. the rising edge of clk is ignored and an internal rising edge is generated by a phase-locked loop. the input clock duty cycle can vary from 30% to 70% and the clock duty cycle stabilizer will maintain a constant 50% internal duty cycle. if the clock is turned off for a long period of time, the duty cycle stabilizer circuit will require one hundred clock cycles for the pll to lock onto the input clock. to use the clock duty cycle stabilizer, the mode pin must be connected to 1/3v dd or 2/3v dd using external resistors. the lower limit of the LTC2201 sample rate is determined by droop of the sample and hold circuits. the pipelined architecture of this adc relies on storing analog signals on small valued capacitors. junction leakage will discharge the capacitors. the speci? ed minimum operating frequency for the LTC2201 is 1msps. figure 8. sinusoidal single-ended clk drive clk 0.1f 0.1f 4.7f 1k 1k ferrite bead clean 3.3v supply sinusoidal clock input 2201 f08 nc7svu04 56 LTC2201 pga pin the pga pin selects between two gain settings for the adc front-end. pga = 0 selects an input range of 2.5v p-p ; pga = 1 selects an input range of 1.667v p-p . the 2.5v input range has the best snr; however, the distortion will be higher for input frequencies above 100mhz. for applications with high input frequencies, the low input range will have improved distortion; however, the snr will be 2.4db worse. see the typical performance characteristics section. driving the clock input the clk input can be driven directly with a cmos or ttl level signal. a sinusoidal clock can also be used along with a low-jitter squaring circuit before the clk pin (figure 8). the noise performance of the LTC2201 can depend on the clock signal quality as much as on the analog input. any noise present on the clock signal will result in additional aperture jitter that will be rms summed with the inherent adc aperture jitter. applications information
LTC2201 17 2201f data format the LTC2201 parallel digital output can be selected for offset binary or 2s complement format. the format is selected with the mode pin. this pin has a four level logic input, centered at 0, 1/3v dd , 2/3v dd and v dd . an external resis- tor divider can be user to set the 1/3v dd and 2/3v dd logic levels. table 1 shows the logic states for the mode pin. table 1. mode pin function mode output format clock duty cycle stabilizer 0(gnd) offset binary off 1/3v dd offset binary on 2/3v dd 2s complement on v dd 2s complement off over? ow bit an over? ow output bit (of) indicates when the converter is over-ranged or under-ranged. a logic high on the of pin indicates an over? ow or under? ow. output clock the adc has a delayed version of the clk input available as a digital output. both a noninverted version, clkout + and an inverted version clkout C are provided. the clkout + /clkout C can be used to synchronize the con- verter data to the digital system. this is necessary when using a sinusoidal clock. data can be latched on the rising edge of clkout + or the falling edge of clkout C . clkout + falls and clkout C rises as the data outputs are updated. digital outputs digital output buffers figure 9 shows an equivalent circuit for a single output buffer in cmos mode. each buffer is powered by ov dd and ognd, isolated from the adc power and ground. the additional n-channel transistor in the output driver allows operation down to low voltages. the internal resistor in series with the output makes the output appear as 50 to external circuitry and eliminates the need for external damping resistors. as with all high speed/high resolution converters, the digital output loading can affect the performance. the digital outputs of the LTC2201 should drive a small capaci- tive load to avoid possible interaction between the digital outputs and sensitive input circuitry. the output should be buffered with a device such as a alvch16373 cmos latch. for full speed operation the capacitive load should be kept under 10pf. a resistor in series with the output may be used but is not required since the adc has a series resistor of 43 on chip. lower ov dd voltages will also help reduce interference from the digital outputs. 2201 f09 ov dd v dd v dd 0.1f typical data output ognd 43 ov dd 0.5v to 3.6v predriver logic data from latch LTC2201 figure 9. equivalent circuit for a digital output buffer applications information
LTC2201 18 2201f digital output randomizer interference from the adc digital outputs is sometimes unavoidable. interference from the digital outputs may be from capacitive or inductive coupling or coupling through the ground plane. even a tiny coupling factor can result in discernible unwanted tones in the adc output spectrum. by randomizing the digital output before it is transmitted off chip, these unwanted tones can be randomized, trading a slight increase in the noise ? oor for a large reduction in unwanted tone amplitude. the digital output is randomized by applying an exclu- sive-or logic operation between the lsb and all other data output bits. to decode, the reverse operation is applied; that is, an exclusive-or operation is applied between the lsb and all other bits. the lsb, of and clkout output are not affected. the output randomizer function is active when the rand pin is high. t t t clkout of d15/d0 d14/d0 d2/d0 d1/d0 d0 d0 d1 rand = high, scramble enabled d2 d14 d15 of clkout rand 2201 f10 LTC2201 figure 10. functional equivalent of digital output randomizer output driver power separate output power and ground pins allow the output drivers to be isolated from the analog circuitry. the power supply for the digital output buffers, ov dd , should be tied to the same power supply as for the logic being driven. for example, if the converter is driving a dsp powered by a 1.8v supply, then ov dd should be tied to that same 1.8v supply. in cmos mode ov dd can be powered with any logic voltage up to 3.6v. ognd can be powered with any voltage from ground up to 1v and must be less than ov dd . the logic outputs will swing between ognd and ov dd . applications information figure 11. descrambling a scrambled digital output t t t d1 d0 d2 d14 d15 pc board fpga clkout of d15/d0 d14/d0 d2/d0 d1/d0 d0 2201 f11 LTC2201
LTC2201 19 2201f figure 12. functional equivalent block diagram of internal dither circuit s/h amp digital summation output drivers multibit deep pseudo-random number generator 16-bit pipelined adc core precision dac clock/duty cycle control clkout + clkout C of d15 t t t d0 clk dither enable high = dither on low = dither off dith analog a in + a in C input 2201 f12 LTC2201 internal dither the LTC2201 is a 16-bit adc with a very linear transfer function; however, at low input levels even slight imperfec- tions in the transfer function will result in unwanted tones. small errors in the transfer function are usually a result of adc element mismatches. an optional internal dither mode can be enabled to randomize the inputs location on the adc transfer curve, resulting in improved sfdr for low signal levels. as shown in figure 12, the output of the sample-and-hold ampli? er is summed with the output of a dither dac. the dither dac is driven by a long sequence pseudo-random number generator; the random number fed to the dither dac is also subtracted from the adc result. if the dither dac is precisely calibrated to the adc, very little of the dither signal will be seen at the output. the dither signal that does leak through will appear as white noise. the dither dac is calibrated to result in less than 0.5db elevation in the noise ? oor of the adc, as compared to the noise ? oor with dither off. grounding and bypassing the LTC2201 require a printed circuit board with a clean unbroken ground plane; a multilayer board with an internal ground plane is recommended. the pinout of the LTC2201 has been optimized for a ? owthrough layout so that the interaction between inputs and digital outputs is minimized. layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. in particular, care should be taken not to run any digital track alongside an analog signal track or underneath the adc. high quality ceramic bypass capacitors should be used at the v dd , v cm , and ov dd pins. bypass capacitors must be located as close to the pins as possible. the traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. the LTC2201 differential inputs should run parallel and close to each other. the input traces should be as short as possible to minimize capacitance and to minimize noise pickup. heat transfer most of the heat generated by the LTC2201 is transferred from the die through the bottom-side exposed pad. for good electrical and thermal performance, the exposed pad must be soldered to a large grounded pad on the pc board. it is critical that the exposed pad and all ground pins are connected to a ground plane of suf? cient area with as many vias as possible. applications information
LTC2201 20 2201f 9 20 20 8 7 6 5 4 3 2 1 a7 v cc u2 74vcx245bqx u1* exposed pad ovp ovp a6 a5 a4 a3 a2 a1 a0 b7 2 4 3 1 5 3 2 1 b6 b5 b4 b3 b2 b1 b0 10 9 8 7 6 5 4 3 2 1 10 11 12 13 14 15 16 17 18 19 11 12 13 14 15 16 17 18 19 gnd j1 3201s-40g1 u6 24lc025 u5 nc7sv86p5x u4 nc7sv86p5x 1 rn1a, 33 rn1b, 33 rn1c, 33 rn1d, 33 rn2a, 33 rn2b, 33 rn2c, 33 rn2d, 33 rn3a, 33 rn3b, 33 rn3c, 33 rn3d, 33 rn4a, 33 rn4b, 33 rn4c, 33 rn4d, 33 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 v cc u3 74vcx245bqx ovp 8 1 2 7 6 5 1 5 3 4 2 3 4 v cc wp scl sda a0 r17 10k r18 10k r19 10k r5 33 a1 a2 a3 a7 a6 a5 a4 a3 a2 a1 a0 b7 b6 b5 b4 b3 b2 b1 b0 gnd oe t/r oe t/r ov dd d11 d10 d9 d8 ognd clkout + clkout C d7 d6 d5 ov dd sense c1 0.1f vcm v dd v dd gnd ain + ain C gnd gnd/enc + gnd/enc C gnd v dd 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 gnd pga rand mode oe of d15 d14 d13 d12 ognd ov dd 13 14 15 16 17 18 19 20 21 22 23 24 49 48 47 46 45 44 43 42 41 40 39 38 37 v dd v dd gnd shdn dith d0 d1 d2 d3 d4 ognd ov dd jp6 dith v dd v dd v dd 3 2 1 gnd jp6 dith v dd 3 3 j3 1 2 4 r20 10k r21 10k 2 1 gnd c19 0.1f c14 0.1f gnd c18 0.1f c17 0.1f c8 2.2f c2 2.2f c16 0.1f c15 0.1f c28 0.1f c13 0.1f ognd 1 2 3 4 8 7 1 6 5 v dd ovp ovp e3 e1 e4 u7 lt1763 r25 out adj gnd v dd + 3.3v r29 1k r30 open r28 33 encode input gnd byp in gnd gnd shdn c21 0.01f c22 1.0f c20 10f 6.3v c27 100f 6.3v opt c23 4.7f r23 100k r22 105k + v dd osc1 opt. v dd v dd r33 * en f o gnd c9 0.1f c3 8.2pf c5 8.2pf c7 8.2pf j4 j2 r12 open r11 open r24 open r32 0 r27 10 r8 51 5.1 r10 5.1 r9 open r26 10 1 2 3 5 t1 analog input dcin+ etc1-1t 4 c4 c6 c26 0.1f c25 0.1f 2201 f013 open v dd jp2 sense jp4 rand jp3 pga v dd v dd r31 o v dd 2 1 2 2 r6 open r7 1k r1 10k r2 10k r3 1k r4 open ovp gnd 33 gnd gnd assembly type * version table u1 r33 input frequency bits msps dc919a-a ltc2207cuk 0.01f dc < a in < 70mhz 16 105 dc919a-b ltc2206cuk 0.01f dc < a in < 70mhz 16 80 dc919a-c ltc2205cuk 0.01f dc < a in < 70mhz 16 65 dc919a-d ltc2204cuk 0.01f dc < a in < 70mhz 16 40 dc919a-e ltc2203cuk 0 dc < a in < 70mhz 16 25 dc919a-f ltc2202cuk 0 dc < a in < 70mhz 16 10 dc919a-g LTC2201cuk 0 dc < a in < 70mhz 16 20 open open r13 open evaluation circuit schematic of the LTC2201 applications information
LTC2201 21 2201f silkscreen top silkscreen topside applications information inner layer 2 inner layer 3
LTC2201 22 2201f silkscreen bottom side silkscreen bottom applications information
LTC2201 23 2201f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description 7.00 0.10 (4 sides) note: 1. drawing conforms to jedec package outline mo-220 variation (wkkd-2) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side, if present 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (see note 6) pin 1 chamfer c = 0.35 0.40 0.10 4847 1 2 bottom viewexposed pad 5.50 ref (4-sides) 0.75 0.05 r = 0.115 typ 0.25 0.05 0.50 bsc 0.200 ref 0.00 C 0.05 (uk48) qfn 0406 rev c recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 0.05 5.50 ref (4 sides) 6.10 0.05 7.50 0.05 0.25 0.05 0.50 bsc package outline 5.15 0.10 5.15 0.10 5.15 0.05 5.15 0.05 r = 0.10 typ uk package 48-lead plastic qfn (7mm 7mm) (reference ltc dwg # 05-08-1704 rev c) please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
LTC2201 24 2201f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear.com linear technology corporation 2012 lt 0412 ? printed in usa part number description comments ltc2202 16-bit, 10msps, 3.3v adc 140mw, 81.6db snr, 100db sfdr, 48-pin qfn ltc2203 16-bit, 25msps, 3.3v adc 220mw, 81.6db snr, 100db sfdr, 48-pin qfn ltc6404-1 600mhz low noise, low distortion, differential adc driver 1.5nv/ hz noise, C90dbc distortion at 10mhz lt1994 low noise, low distortion fully differential input/output ampli? er/driver low distortion: C94dbc at 1mhz ltc2204 16-bit, 40msps, 3.3v adc 480mw, 79.1db snr, 100db sfdr, 48-pin qfn ltc2205 16-bit, 65msps, 3.3v adc 610mw, 79db snr, 100db sfdr, 48-pin qfn ltc2206 16-bit, 80msps, 3.3v adc 725mw, 77.9db snr, 100db sfdr, 48-pin qfn ltc2207 16-bit, 105msps, 3.3v adc 900mw, 77.9db snr, 100db sfdr, 48-pin qfn ltc2208 16-bit, 130msps, 3,3v adc, lvds outputs 1250mw, 77.1db snr, 100db sfdr, 64-pin qfn ltc2224 12-bit, 135msps, 3.3v adc, high if sampling 630mw, 67.6db snr, 84db sfdr, 48-pin qfn ltc2242-12 12-bit, 250msps, 2.5v adc, lvds outputs 740mw, 65.4db snr, 84db sfdr, 64-pin qfn ltc2255 14-bit, 125msps, 3v adc, lowest power 395mw, 72.5db snr, 88db sfdr, 32-pin qfn ltc2284 14-bit, dual, 105msps, 3v adc, low crosstalk 540mw, 72.4db snr, 88db sfdr, 64-pin qfn lt5512 dc-3ghz high signal level downconverting mixer dc to 3ghz, 21dbm iip3, integrated lo buffer lt5514 ultralow distortion if ampli? er/adc driver with digitally controlled gain 450mhz to 1db bw, 47db oip3, digital gain control 10.5db to 33db in 1.5db/step lt5515 1.5ghz to 2.5ghz direct conversion quadrature demodulator high iip3: 20dbm at 1.9ghz, integrated lo quadrature generator lt5516 800mhz to 1.5ghz direct conversion quadrature demodulator high iip3: 21.5dbm at 900mhz, integrated lo quadrature generator lt5517 40mhz to 900mhz direct conversion quadrature demodulator high iip3: 21dbm at 800mhz, integrated lo quadrature generator lt5522 600mhz to 2.7ghz high linearity downconverting mixer 4.5v to 5.25v supply, 25dbm iip3 at 900mhz. nf = 12.5db, 50 single ended rf and lo ports related parts

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